In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, data are placed on a data bus by the memory device in synchronism with the external clock signal, and the memory device must provide the data at the proper times for the data to be valid. To provide the data at the correct times, an internal clock signal is developed in response to the external clock signal, and is typically applied to data latches in the memory device to thereby clock the data onto the data bus. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully output the data at the proper times. In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. To increase the rate at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 100 MHz. As the frequency of the external clock signal increases, however, the delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the data applied to the data bus may not be valid at the proper times to be latched.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another. FIG. 1 is a functional block diagram illustrating a conventional delay-locked loop 100 including a variable delay line 102 that receives a clock buffer signal CLKBUF and generates a delayed clock signal CLKDEL in response to the clock buffer signal. The variable delay line 102 controls a variable delay VD of the CLKDEL signal relative to the CLKBUF signal in response to a delay adjustment signal DADJ. As shown in FIG. 1, the variable delay 102 includes a bank of registers and a delay line. The delay line of the variable delay 102 includes a plurality of delay stages (not shown) that can be individually activated and deactivated to incrementally increase and decrease the variable delay VD by a delay tD. The bank of registers is used to store a value represented by the DADJ signal that corresponds to the number of delay stages that are activated. In order to change the delay of the variable delay VD, the value stored by the bank of registers should be changed.
A feedback delay line 104 generates a feedback clock signal CLKFB in response to the CLKDEL signal, the feedback clock signal having a model delay D1+D2 relative to the CLKDEL signal. The D1 component of the model delay D1+D2 corresponds to a delay introduced by an input buffer 106 that generates the CLKBUF signal in response to an external clock signal CLK, while the D2 component of the model delay corresponds to a delay introduced by an output buffer 108 that generates a synchronized clock signal CLKSYNC in response to the CLKDEL signal. Although the input buffer 106 and output buffer 108 are illustrated as single components, each represents all components and the associated delay between the input and output of the delay-locked loop 100. The input buffer 106 thus represents the delay D1 of all components between an input that receives the CLK signal and the input to the variable delay line 102, and the output buffer 108 represents the delay D2 of all components between the output of the variable delay line and an output at which the CLKSYNC signal is developed. For example, the output buffer 108 may represent all of components in a data path in the memory device through which the data propagates to be provided onto the data bus. The CLKSYNC signal can then be used to clock the output data latches such that the data is provided in synchronicity with the CLK signal applied to the memory device.
The delay-locked loop 100 further includes a phase detector 110 that receives the CLKFB and CLKBUF signals and generates a delay control signal SL/SR that is based on the phase difference between the CLKBUF and CLKFB signals. A delay controller 112 generates the DADJ signal in response to the SL/SR signal from the phase detector 110, and applies the DADJ signal to the variable delay line 102 to adjust the variable delay VD. The phase detector 110 and delay controller 112 operate in combination to adjust the variable delay VD of the variable delay line 102 as a function of the detected phase between the CLKBUF and CLKFB signals. As previously discussed, the variable delay line 102 includes a bank of registers that stores a value represented by the DADJ signal that corresponds to the number of delay stages that are activated. The delay stages can be conceptualized as a chain of delay stages that are activated in a “left-to-right” manner, with each of the activated delay stages adding an incremental delay to the variable delay VD. The SL/SR signal generated by the phase detector 110 represents a “shift left” (SL) or “shift right” (SR) command that is used by the delay controller to increase or decrease, respectively, the variable delay VD of the variable delay line 102. That is, each SL signal from the phase detector 110 will be used by the delay controller 112 to incrementally increase the variable delay VD and each SR signal from the phase detector 110 will be used by the delay controller 112 to incrementally decrease the variable delay VD.
FIG. 2 illustrates an example of the phase detector 110. The phase detector 110 includes a first fixed delay 256 that provides a delay of tPDW to the CLKFB signal to generate a delayed feedback clock signal CLKFB2D. A second fixed delay 258 provides a delay of tPDW/2, that is, half of the delay provided by the first fixed delay 256, to the CLKBUF signal to generate a delayed reference clock signal CLKBUFD. The CLKBUFD signal is used to clock a set of D flip-flops 260, 262 which sample the CLKFB signal and the CLKFB2D signal. The D flip-flops 262 and 260 output signals PH1 and PH2, respectively, to a majority filter 266. The values of the PH1 and PH2 signals at any given instant are indicative of the phase of the CLKFB signal with respect to the CLKBUF signal. The phase relationship between the PH1 and PH2 signals are used to determine whether to lengthen or shorten the variable delay VD of the variable delay line 102 (FIG. 1).
The majority filter 266 coupled to the D flip-flops 260, 262 generates the SL/SR signal based on the PH1 and PH2 signals and in response to a counting clock signal COUNTCLK. The CLK or CLKBUF signals can be used for the COUNTCLK signal. The majority filter 266 typically includes a binary up/down counter (not shown) that is clocked by the COUNTCLK signal and counts up or down based on the values of PH1 and PH2 signals. Typically, in an effort to reduce jitter of the SL/SR signal, the majority filter 266 is designed to switch the state of the SL/SR signal only after the up/down counter is incremented or decremented a fixed number. For example, before the up/down counter generates a SL/SR signal to adjust the variable delay VD, the up/down counter must count up or down for four cycles (c=4) of the COUNTCLK signal.
The operation of the DLL 100 will now be described with reference to FIG. 1. The phase detector 110 detects the phase difference between the CLKBUF and CLKFB signals, and the phase detector and delay controller 112 operate in combination to adjust the variable delay VD of the CLKDEL signal until the phase difference between the CLKBUF and CLKFB signals is approximately zero. More specifically, as the variable delay VD of the CLKDEL signal is adjusted, the phase of the CLKFB signal from the feedback delay line 104 is adjusted accordingly until the CLKFB signal has approximately the same phase as the CLKBUF signal. When the delay-locked loop 100 has adjusted the variable delay VD to a value causing the phase shift between the CLKBUF and CLKFB signals to equal approximately zero, the delay-locked loop is said to be “locked.” When the delay-locked loop 100 is locked, the CLK and CLKSYNC signals are synchronized. This is true because when the phase shift between the CLKBUF and CLKFB signals is approximately zero (i.e., the delay-locked loop 100 is locked), the variable delay VD has a value of NTCK−(D1+D2) as indicated in FIG. 1, where N is an integer and TCK is the period of the CLK signal. When VD equals NTCK−(D1+D2), the total delay of the CLK signal through the input buffer 106, variable delay line 102, and output buffer 108 is D1+NTCK−(D1+D2)+D2, which equals NTCK. Thus, the CLKSYNC signal is delayed by NTCK relative to the CLK signal and the two signals are synchronized since the delay is an integer multiple of the period of the CLK signal. Referring back to the discussion of synchronous memory devices above, the CLK signal corresponds to the external clock signal and the CLKSYNC signal corresponds to the internal clock signal.
After the DLL 100 is reset, for example, when the DLL 100 is initialized or restarted after exiting a sleep mode, the variable delay VD of the variable delay line 102 is typically set to its minimum delay. In order to obtain a lock condition, the variable delay VD is incrementally increased from the minimum delay to a delay under the control of the phase detector 110 that will provide a lock condition. As previously discussed, the variable delay VD is incrementally increased by adding fixed increments of delay through the use of the delay stages in the variable delay line 102. With the phase detector 110 comparing the phases of the CLKBUF and CLKFB signals, an intrinsic delay tID exists between when an adjustment is made to the variable delay VD and when the CLKFB signal having the additional delay is detected by the phase detector 110 and compared with the CLKBUF signal. The length of tID is in part based on the delay of the variable delay VD and the feedback delay line 104. As a result, the variable delay VD is increased by the incremental delay of one delay stage after the intrinsic delay tID has elapsed. The design of the majority filter 266, which generates an SL/SR signal to increment the delay of the variable delay line 102 only after a number of clock cycles of the COUNTCLK signal, further adds to the time required to obtain a lock condition. As a result, the process of obtaining a lock condition with the DLL 100 typically takes several iterations of incrementally adding a delay and detecting whether sufficient delay has been added. In the case where significant delay must be added to obtain a lock condition, the process of incrementally adding the delay will take considerable time. As performance specifications for obtaining a lock condition are often defined in the number of clock cycles elapsed, the time for obtaining a lock condition may be tolerable for lower frequency CLK signals that have clock periods comparable to the intrinsic delay tID. However, using higher frequency CLK signals having clock periods that are a fraction of the intrinsic delay tID may result in an unacceptable number of clock cycles required to obtain a lock condition.
One approach to decreasing the lock time for a DLL is to automatically increment the variable delay VD every clock cycle, or every other clock cycle of the CLK signal following initialization, to quickly increase the variable delay VD until phase detector 110 detects that the CLKBUF and CLKFB signals are synchronized. Although forcing the variable delay VD to increase incrementally every clock cycle can decrease locking time, there may be overshoot in the variable delay VD for higher frequency CLK signals. That is, due to the intrinsic delay tID, the variable delay VD may continue to be incrementally increased even after the variable delay VD is sufficient to provide a lock condition, as detected by the phase detector 110. In the event of overshooting the appropriate delay, the variable delay VD will need to be decreased to return to the appropriate delay to obtain a lock condition. The process of decrementing the variable delay VD will suffer from the same issues as for incrementing the variable delay VD after initialization, that is, it will take several clock cycles to complete the process because of the intrinsic delay tID and the design of the majority filter 266 (FIG. 2).
Therefore, there is a need for a DLL having the ability to quickly obtain a lock condition following initialization.